NTP3000 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'NTP3000' PDF : 37 Pages View PDF
Power Integrated Processor for Digital Amplifier
NTP3000
Table 5 Level dependent master volume steps
Step
Range
0.5 dB
+24 ~ -100 dB
10dB
-100 ~ -150 dB
9.2. Channel Volume Control
By setting volume control registers, channel volumes are independently controlled between infinity and
+24dB with changing step size as described below, and in the Appendix 2, exact values for channel
volume setting are described.
Table 6 Level dependent channel volume steps
Step
Range
0.5 dB
+24 ~ -100 dB
10dB
-100 ~ -150 dB
9.3. Master Volume Fine Control
Fine control for master volume is possible (+0.0625dB step upto maximum +0.4375dB boost). Refer the
system register Address 0x2D in the Appendix 1.
9.4. Master Volume Override
By setting the master volume override flag on each channel, the master volume is not applied to the
configured channels. See the system register Address 0x0A in the Appendix 1.
9.5. Mute
NTP3000 enters mute state by setting soft mute flag of register Address 0x20. Soft mute is implemented
so that the volume gradually increases or decreases when mute is turned off or on respectively.
Also the soft mute speed and soft volume change speed rates are programmable. Designers can
minimize the pop noise by controlling the soft mute speed and volume change intervals. Refer SMC, SVI
flag of register Address 0x06.
9.6. Auto-mute
The chip mutes audio signal if the input signal level is below auto mute threshold during auto mute
inspection interval that are programmable by register setting. Also, the behavior when auto mute has
been entered is changeable between 50:50 switching on or off.
Auto-mute is supported for internal channels 1~3 after 2x3 mixer block. Refer register Addresses 0x04
and 0x05.
9.7. Dynamic Range Control
Dynamic range compression can be turned on or off with programmable compression threshold and
attack/release rates. The threshold parameters of DRC can be controlled separately for channel 1/2 and
channel 3. For detailed setting, please refer system register Addresses 0x0E~10.
Copyright © NeoFidelity, Inc. 2005
Preliminary datasheet – NeoFidelity reserves the right to change specifications at any time without prior notice
16
R0.73-11.2006
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