NTP3000 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'NTP3000' PDF : 37 Pages View PDF
Power Integrated Processor for Digital Amplifier
NTP3000
A1. Configuration Register Summary
Table 8 Address 0x00: Input Format
Bit
7
6
5
Name
X
X
X
Name
INS
FSM
Description
Input format
Sampling
Frequency
in Master mode IIS
Value
00
01
10
11
000
001
010
011
100
101
110
111
4
3
2
FSM
1
0
INS
Meaning
Ref.
I2S, slave mode
I2S, master mode
General serial audio, slave mode
General serial audio, master mode
48 kHz
8 kHz
16 kHz
32 kHz
12 kHz
24 kHz
96 kHz
192 kHz
Table 9 Address 0x01: General Serial Audio Format
Bit
7
6
5
4
3
2
Name
X
X
BCKS
BS
Name
LRJ
MLF
BS
BCKS
Description
Serial data justify
Serial bit order
Serial bit size
Bit clock size select
Value
0
1
0
1
00
01
10
11
00
01
10
Left justify
Right justify
MSB first
LSB first
24 bit
20 bit
18 bit
16 bit
64 BCK/WCK
48 BCK/WCK
32 BCK/WCK
Meaning
1
0
MLF
LRJ
Ref.
Table 10 Address 0x02: Master clock frequency control
Bit
7
6
5
4
3
2
1
0
Name
X
X
X
X
X
X
MCF
Name
MCF
Description
Master Clock
Frequency
Value
00
01
10
11
Meaning
12.288 MHz
24.576 MHz
18.432 MHz
User defined frequency. Required to set
address 0x7D and address 0x7E first.
Ref.
See
Table
Copyright © NeoFidelity, Inc. 2005
Preliminary datasheet – NeoFidelity reserves the right to change specifications at any time without prior notice
19
R0.73-11.2006
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