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P3C1024L View Datasheet(PDF) - Semiconductor Corporation

Part Name
Description
MFG CO.
P3C1024L
PYRAMID
Semiconductor Corporation PYRAMID
'P3C1024L' PDF : 10 Pages View PDF
1 2 3 4 5 6 7 8 9 10
P3C1024L
READ CYCLE NO. 1 (OE CONTROLLED)(1)
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
READ CYCLE NO. 3 (CE CONTROLLED)
Notes:
1. WE is HIGH for READ cycle.
2.
CE
1
and
OE
is LOW, and CE2 is HIGH for READ cycle.
3. ADDRESS must be valid prior to, or coincident with later of
CE
1
transition
LOW
or
CE2
transition
HIGH.
4. Transition is measured ± 200 mV from steady state voltage prior
to change, with loading as specified in Figure 1. This parameter
is sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the
first transitioning address.
Document # SRAM132 REV OR
Page 4 of 9
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