P3C1024L View Datasheet(PDF) - Semiconductor Corporation
Part Name
Description
MFG CO.
'P3C1024L' PDF : 10 Pages View PDF
P3C1024L
DATA RETENTION
Symbol
Parameter
Test Conditions
Min
V
V for Data Retention
DR
CC
CE
1
≥
VCC
-0.2V,
CE2
≤
0.2V,
VIN ≥ VCC -0.2V or VIN ≤ 0.2V
2.0
I
(1)
CCDR
Data Retention Current
V = 2.0V
DR
tCDR
Chip Deselect to Data
See Retention Waveform
0
Retention Time
t
Operating Recovery Time(2)
100
R
1.
CE
1
≥
VDR
-0.2V,
CE2
≥
VDR
-0.2V
or
CE2
≤
0.2V;
or
CE
1
≤
0.2V,
CE2
-
0.2V;
VIN
≥
VDR
-0.2V
or
VIN
≤
0.2V
2. VCC ramp from VDR to VCC (min) > 100 µs for full device operation.
Max Unit
V
10 µA
ns
µs
LOW VCC DATA RETENTION WAVEFORM 1 (CE1 CONTROLLED)
LOW V DATA RETENTION WAVEFORM 2 (CE CONTROLLED)
CC
2
Document # SRAM132 REV OR
Page 7 of 9
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