P521-39DC View Datasheet(PDF) - PhaseLink Corporation
Part Name
Description
MFG CO.
'P521-39DC' PDF : 6 Pages View PDF
Preliminary P521-39
Low Phase Noise LVDS VCXO (65MHz to 130MHz)
4. General Electrical Specifications
PARAMETERS
Supply Current (Loaded Outputs)
Output valid after OE enabled
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
SYMBOL
CONDITIONS
IDD
at 3.3V @ 77.76MHz
Oscillator off
Oscillator on
VDD
@ 1.25V (LVDS)
MIN.
2.25
45
TYP.
10
50
±50
MAX.
40
1
3.63
55
UNITS
mA
ms
V
%
mA
5. Jitter specifications
PARAMETERS
CONDITIONS
Period jitter RMS at 77.76MHz
Period jitter peak-to-peak at 77.76MHz
Accumulated jitter RMS at 77.76MHz
Accumulated jitter peak-to-peak at 77.76MHz
Random Jitter
Integrated jitter RMS at 77.76MHz
Measured on Wavecrest SIA 3000
At 77.76MHz, with capacitive
decoupling between VDD and GND.
Over 10,000 cycles
At 77.76MHz, with capacitive
decoupling between VDD and GND.
Over 1,000,000 cycles.
“RJ” measured on Wavecrest SIA 3000
Integrated 12 kHz to 20 MHz
MIN.
TYP.
2.5
18.5
2.5
24
2.5
0.5
MAX. UNITS
ps
20
ps
27
ps
0.7
ps
6. Phase noise specifications
PARAMETERS FREQUENCY
Phase Noise
relative to carrier
77.76MHz
Note: Phase Noise measured at VCON = 0V
10Hz
-75
100Hz
-100
1kHz
-125
10kHz
-140
100kHz
-145
1MHz
-150
UNITS
dBc/Hz
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 3/02/04 Page 4
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