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P89C738ABB View Datasheet(PDF) - Philips Electronics

Part Name
Description
MFG CO.
P89C738ABB
Philips
Philips Electronics Philips
'P89C738ABB' PDF : 64 Pages View PDF
Philips Semiconductors
8-bit Flash microcontrollers
Product specification
P89C738; P89C739
10.3 Watchdog Timer (T3)
The Watchdog Timer (see Fig.14), consists of an 11-bit
prescaler and an 8-bit timer formed by SFR T3. The timer
is incremented every 1.5 ms, which is derived from the
system clock frequency of 16 MHz by the following
formula: ftimer = --(--1---2-----×-f--c--2-l-k-0----4---8----)-
The 8-bit timer increments every 12 × 2048 cycles of the
on-chip oscillator. When a timer overflow occurs, the
microcontroller is reset. The internal reset signal is not
inhibited when the external RST pin is kept LOW, e.g. by
an external reset circuit. The reset signal drives Ports 1, 2,
3, 4 and 5 outputs into the HIGH state and Port 0 into
high-impedance, no matter whether the clock oscillator is
running or not.
To prevent a system reset the timer must be reloaded in
time by the application software. If the processor suffers a
hardware/software malfunction, the software will fail to
reload the timer. This failure will result in a reset upon
overflow thus preventing the processor running out of
control.
This time interval is determined by the 8-bit reload value
that is written into register T3:
Watchdog time interval = --[--T----3----]----×----f-1-c---l2-k---×-----2----0---4---8--
The Watchdog Timer can only be reloaded if the condition
flag WLE (PCON.4) has been previously set HIGH by
software. At the moment the counter is loaded WLE is
automatically cleared.
In the Idle mode the Watchdog Timer and reset circuitry
remain active.
The Watchdog Timer is controlled by the Watchdog enable
signal EW (EBTCON.1). A HIGH level enables the
Watchdog Timer and disables the Power-down mode.
A LOW level disables the Watchdog Timer and enables
the Power-down mode.
handbook, full pagewidth
1/12 fclk
EW
(1) See Fig.21.
INTERNAL BUS
PRESCALER
11-BIT
CLEAR
TIMER T3 (8-BIT)
LOAD LOADEN
to reset circuitry (1)
write
T3
CLEAR
WLE
PCON.4
INTERNAL BUS
Fig.14 Watchdog Timer block diagram.
PD
LOADEN
PCON.1
MBH081
1998 Apr 07
24
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