P89C738ABB View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'P89C738ABB' PDF : 64 Pages View PDF
Philips Semiconductors
8-bit Flash microcontrollers
Product specification
P89C738; P89C739
13.4 Status of external pins
Table 20 Status of the external pins during Idle and Power-down modes
MODE
Idle
Power-down
MEMORY
internal
external
internal
external
ALE
HIGH
HIGH
LOW
LOW
PSEN
HIGH
HIGH
LOW
LOW
PORT 0
port data
floating
port data
floating
PORT 1
port data
port data
port data
port data
PORT 2
port data
address
port data
port data
PORT 3
port data
port data
port data
port data
PORT 4
port data
port data
port data
port data
PORT 5
port data
port data
port data
port data
13.5 Power Control Register (PCON)
Special modes are activated by software via the SFR PCON. PCON is not bit addressable. The reset value of PCON is
00H.
Table 21 Power Control Register (SFR address 87H)
7
6
5
4
3
2
1
0
SMOD
ARE
RFI
WLE
GF1
GF0
PD
IDL
Table 22 Description of PCON bits
BIT
SYMBOL
DESCRIPTION
7
SMOD Double baud rate bit. When set to a logic 1 the baud rate is doubled when Timer 1 is
used to generate baud rate, and the Serial Port is used in Modes 1, 2 or 3.
6
ARE
AUX-RAM enable bit. When set to a logic 1 the AUX-RAM is disabled, so that all
MOVX-instructions access the external data memory.
5
RFI
Reduced Radio Frequency Interference bit. When set to a logic 1 the toggling of the
ALE pin is prohibited. This bit is cleared on reset. See also Chapters 1 “Features”: on
EMC and 6 “Pinning information”: note 2.
4
WLE Watchdog Load Enable. This flag must be set by software prior to loading the
Watchdog Timer (T3). It is cleared when timer T3 is loaded.
3
GF1
General-purpose flag bit.
2
GF0
1
PD(1) Power-down select. Setting this bit activates the Power-down mode.
0
IDL(1) Idle mode select. Setting this bit activates the Idle mode.
Note
1. If logic 1s are written to PD and IDL at the same time, PD takes precedence.
1998 Apr 07
30
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