P8XCL580HFT View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'P8XCL580HFT' PDF : 80 Pages View PDF
Philips Semiconductors
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
Product specification
P80CL580; P83CL580
13.1 ADC Control Register (ADCON)
Table 9 ADC Control Register (address C4H)
7
6
5
4
−
ADPD
ADEX
ADCI
3
ADCS
2
CKDIV
1
AADR1
0
AADR0
Table 10 Description of ADCON bits
BIT
SYMBOL
DESCRIPTION
7
−
Reserved.
6
ADPD Power-down. This bit switches off the resistor reference to save power even when the
CPU is operating.
5
ADEX Enable external start of conversion. This bit determines whether a conversion can be
started using the external pin STADC. When ADEX = 0, a conversion cannot be started
externally using STADC. When ADEX = 1, a conversion can be started externally using
STADC.
4
ADCI ADC interrupt flag. This flag is set when an ADC conversion result is ready to be read.
An interrupt is invoked if this is enabled. This flag must be cleared by software (it cannot
be set by software); see Table 11.
3
ADCS ADC start and status flag. When this bit is set an ADC conversion is started. ADCS
may be set by software or by the external signal STADC. The ADC logic ensures that
this signal is HIGH while the ADC is busy. On completion of the conversion ADCS is
reset and after that the interrupt flag ADCI is set. ADCS cannot be reset by software;
see Table 11.
2
CKDIV This bit selects the conversion time, in terms of instruction cycles. This allows the CPU
to be run at the maximum frequency (12 MHz) yet keeping the ADC timing at low
frequency. When CKDIV = 0, the conversion time is equivalent to 24 instruction cycles.
When CKDIV = 1, the conversion time is equivalent to 48 instruction cycles.
The conversion time includes a sampling time of 6 cycles.
1
AADR1 Analog input select. These bits are used to select one of the four analog inputs; see
0
AADR0 Table 12. They only can be changed when ADCI and ADCS are both LOW.
Table 11 Analog-to-digital operation
ADCI ADCS
OPERATION
0
0 ADC not busy; a conversion can be
started.
0
1 ADC busy; start of a new conversion is
blocked.
1
0 Conversion completed; start of a new
conversion is blocked.
1
1 Intermediate status for a maximum of
one machine cycle before conversion is
completed (ADCI = 1, ADCS = 0).
Table 12 Selection of analog input channel
AADR1 AADR0
0
0
0
1
1
0
1
1
SELECTED CHANNEL
AD0
AD1
AD2
AD3
1997 Mar 14
24
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