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P8XCL580HFT View Datasheet(PDF) - Philips Electronics

Part Name
Description
MFG CO.
'P8XCL580HFT' PDF : 80 Pages View PDF
Philips Semiconductors
Low voltage 8-bit microcontrollers with
UART, I2C-bus and ADC
Product specification
P80CL580; P83CL580
14.4 Status of external pins
The status of the external pins during Idle and Power-down
mode is shown in Table 13. If the Power-down mode is
activated whilst accessing external Program Memory, the
port data that is held in the Special Function Register P2 is
restored to Port 2.
If the data is a logic 1, the port pin is held HIGH during the
Power-down mode by the strong pull-up transistor ‘p1’;
see Fig.9(a).
Table 13 Status of external pins during Idle and Power-down modes
MODE
Idle
Power-down
MEMORY
internal
external
internal
external
ALE
1
1
0
0
PSEN
1
1
0
0
PWM0
active
active
HIGH
HIGH
PORT 0 PORT 1 PORT 2 PORT 3 PORT 4
port data port data port data port data port data
floating port data address port data port data
port data port data port data port data port data
floating port data port data port data port data
14.5 Power Control Register (PCON)
Idle and Power-down modes are activated by software using this SFR. PCON is not bit addressable, the reset value of
PCON is 0XX00000B.
Table 14 Power Control Register (address 87H)
7
6
SMOD
5
4
3
2
1
0
WLE
GF1
GF0
PD
IDL
Table 15 Description of PCON bits
BIT
7
6 and 5
4
3 and 2
1
0
SYMBOL
DESCRIPTION
SMOD
Double Baud rate bit. When set to a logic 1 the baud rate is doubled when the serial
port SIO0 is being used in modes 1, 2 or 3.
Reserved.
WLE
Watchdog Load Enable. This flag must be set by software prior to loading the
Watchdog Timer (T3). It is cleared when T3 is loaded.
GF1 and GF0 General purpose flag bits.
PD
Power-down bit. Setting this bit activates the Power-down mode. This bit can only be
set if input EWN is HIGH. If a logic 1 is written to both PD and IDL at the same time, PD
takes precedence.
IDL
Idle mode bit. Setting this bit activates the Idle mode.
1997 Mar 14
26
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