PC8533-2 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PC8533-2' PDF : 45 Pages View PDF
NXP Semiconductors
PCF8533
Universal LCD driver for low multiplex rates
The acknowledgement after each byte is made only by the (A0, A1, and A2) addressed
PCF8533. After the last (display) byte, the I2C-bus master asserts a STOP condition (P).
Alternatively a START may be asserted to RESTART an I2C-bus access.
8.2 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. The five
commands available to the PCF8533 are defined in Table 9.
Table 9. Definition of commands
Command
Operation code
Reference
mode-set
1
1
0
0
E
B
M1 M0 Table 10
load-data-pointer
0
P6 P5 P4 P3 P2 P1 P0 Table 11
device-select
1
1
1
0
0
A2 A1 A0 Table 12
bank-select
1
1
1
1
1
0
I
O Table 13
blink-select
1
1
1
1
0
A
BF1 BF0 Table 14
Table 10. Mode-set command bit description
Bit
Symbol Value
Description
7 to 4 -
1100
fixed value
3
E
display status
the possibility to disable the display allows implementation of
blinking under external control
0
disabled (blank)
1
enabled
2
B
LCD bias configuration
1 to 0
0
1
M[1:0]
1⁄3 bias
1⁄2 bias
LCD drive mode selection
01
static; 1 backplane
10
1:2 multiplex; 2 backplanes
11
1:3 multiplex; 3 backplanes
00
1:4 multiplex; 4 backplanes
Table 11. Load-data-pointer command bit description
See Section 7.11.
Bit
Symbol Value
Description
7
-
0
fixed value
6 to 0
P[6:0]
0000000 to immediate data
1001111 7-bit binary value of 0 to 79, transferred to the data pointer to
define one of 80 display RAM addresses
PCF8533_4
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 5 March 2010
© NXP B.V. 2010. All rights reserved.
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