NXP Semiconductors
PCF8533
Universal LCD driver for low multiplex rates
Table 22. Bump locations
All x/y coordinates represent the position of the centre of each bump with respect to the center
(x/y = 0) of the chip; see Figure 25.
Symbol Bump X (μm) Y (μm)
Description
A0
10
249.20 −594.40
subaddress input
A1
11
379.20 −594.40
A2
12
581.20 −594.40
SA0
13
711.20 −594.40
I2C-bus slave address input; bit 0
VSS
14
841.20 −594.40
VLCD
15
1099.60 −594.40
BP2
16
1277.60 −594.40
ground supply voltage
LCD supply voltage
LCD backplane output
BP0
17
1357.60 −594.40
S0
18
1437.60 −594.40
S1
19
1517.60 −594.40
S2
20
1597.60 −594.40
S3
21
1677.60 −594.40
S4
22
1757.60 −594.40
S5
23
1837.60 −594.40
S6
24
1917.60 −594.40
S7
25
1997.60 −594.40
S8
26
2077.60 −594.40
S9
27
2157.60 −594.40
S10
28
2237.60 −594.40
S11
29
2317.60 −594.40
LCD segment output
S12
30
2357.60 594.40
S13
31
2277.60 594.40
S14
32
2197.60 594.40
S15
33
2117.60 594.40
S16
34
2037.60 594.40
S17
35
1957.60 594.40
S18
36
1877.60 594.40
S19
37
1797.60 594.40
S20
38
1717.60 594.40
S21
39
1637.60 594.40
S22
40
1557.60 594.40
S23
41
1477.60 594.40
S24
42
1317.60 594.40
S25
43
1237.60 594.40
S26
44
1157.60 594.40
S27
45
1077.60 594.40
S28
46
997.60 594.40
S29
47
917.60 594.40
PCF8533_4
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 5 March 2010
© NXP B.V. 2010. All rights reserved.
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