NXP Semiconductors
PCF8533
Universal LCD driver for low multiplex rates
Table 22. Bump locations
All x/y coordinates represent the position of the centre of each bump with respect to the center
(x/y = 0) of the chip; see Figure 25.
Symbol Bump X (μm) Y (μm)
Description
S67
85
−2362.40 594.40
LCD segment output
S68
86
−2322.40 −594.40
S69
87
−2242.40 −594.40
S70
88
−2162.40 −594.40
S71
89
−2082.40 −594.40
S72
90
−2002.40 −594.40
S73
91
−1922.40 −594.40
S74
92
−1842.40 −594.40
S75
93
−1762.40 −594.40
S76
94
−1682.40 −594.40
S77
95
−1602.40 −594.40
S78
96
−1522.40 −594.40
S79
97
−1442.40 −594.40
BP3
98
−1362.40 −594.40
LCD backplane output
BP1
99
−1282.40 −594.40
D1
-
2469.70 −594.40
[2] dummy bump
D2
-
2549.70 −594.40
D3
-
2517.60 594.40
D4
-
2437.60 594.40
D5
-
−2442.30 594.40
D6
-
−2522.30 594.40
[2]
D7
-
−2554.40 −594.40
D8
-
−2474.40 −594.40
[1] For most applications SDA and SDAACK are shorted together; see Section 8.1.
[2] The dummy bumps are connected to the adjacent segments but are not tested.
PCF8533_4
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 5 March 2010
© NXP B.V. 2010. All rights reserved.
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