PCF2113 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF2113' PDF : 65 Pages View PDF
NXP Semiconductors
PCF2113x
LCD controllers/drivers
RS
R/W
E
internal
internal operation
DB7
IR7 IR3
busy AC3
instruction
write
busy flag
check
IR7, IR3: instruction 7th, 3rd bit.
AC3: address counter 3rd bit.
D7, D3: data 7th, 3rd bit.
Fig 23. Example of 4-bit data transfer timing sequence
not
busy AC3
busy flag
check
D7 D3
instruction
write mga805
RS
R/W
E
internal
internal operation
DB7
data
busy
busy
instruction
write
busy flag
check
busy flag
check
Fig 24. Example of busy flag checking timing sequence
not
busy
busy flag
check
data
instruction
write
mga806
11.2 I2C-bus interface
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are the Serial Data line (SDA) and the Serial Clock Line (SCL). Both lines
must be connected to a positive supply via pull-up resistors. Data transfer may be initiated
only when the bus is not busy.
Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH
level signal put on the bus by the transmitter during which time the master generates an
extra acknowledge related clock pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte.
PCF2113_FAM_4
Product data sheet
Rev. 04 — 4 March 2008
© NXP B.V. 2008. All rights reserved.
37 of 65
Share Link: 
