PCF2113 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF2113' PDF : 65 Pages View PDF
NXP Semiconductors
PCF2113x
LCD controllers/drivers
Also a master receiver must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge
related clock pulse (set-up and hold times must be taken into consideration).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge bit on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
11.2.1 I2C-bus protocol
Before any data is transmitted on the I2C-bus, the device which should respond is
addressed first. The addressing is always carried out with the first byte transmitted after
the START procedure. The I2C-bus configuration for the different PCF2113x read and
write cycles is shown in Figure 25, Figure 26 and Figure 27. The slow-down feature of the
I2C-bus protocol (receiver holds SCL LOW during internal operations) is not used in the
PCF2113x.
acknowledgement
from PCF2113x
S
S 0 1 1 1 0 1 A 0 A 1 RS CONTROL BYTE A
0
DATA BYTE
slave address
R/W Co
2n ≥ 0 bytes
A 0 RS CONTROL BYTE A
1 byte
Co
DATA BYTE
AP
n ≥ 0 bytes
update
data pointer
mgg002
S
011101A0
0
PCF2113x
slave address
R/W
Fig 25. Master transmits to slave receiver; write mode
PCF2113_FAM_4
Product data sheet
Rev. 04 — 4 March 2008
© NXP B.V. 2008. All rights reserved.
38 of 65
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