PCF2123U/5GA/1 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF2123U/5GA/1' PDF : 63 Pages View PDF
NXP Semiconductors
PCF2123
SPI Real time clock/calendar
8.6.4 Countdown timer function
The 8-bit countdown timer at address 0Fh is controlled by the register Timer_clkout at
address 0Eh. The register Timer_clkout selects one of 4 source clock frequencies for the
timer (4.096 kHz, 64 Hz, 1 Hz, or 1⁄60 Hz) and enables or disables the timer.
Table 29. Bits CTD0 and CTD1 for timer frequency selection and countdown timer
durations
CTD[1:0] Timer source clock
frequency[1]
Delay
Minimum timer duration
n=1
Maximum timer duration
n = 255
00
4.096 kHz
244 s
62.256 ms
01
64 Hz
10
1 Hz[2]
11
1⁄60 Hz[2]
15.625 ms
1s
60 s
3.984 s
255 s
4 h 15 min
[1] When not in use, CTD must be set to 1⁄60 Hz for power saving.
[2] Time periods can be affected by correction pulses.
Remark: Note that all timings which are generated from the 32.768 kHz oscillator are
based on the assumption that there is 0 ppm deviation. Deviation in oscillator frequency
will result in deviation in timings. This is not applicable to interface timing.
The timer counts down from a software-loaded 8-bit binary value, n. Loading the counter
with 0 stops the timer. Values from 1 to 255 are valid. When the counter reaches 1, the
countdown timer flag (bit TF) will be set and the counter automatically re-loads and starts
the next timer period. Reading the timer will return the current value of the countdown
counter (see Figure 15).
PCF2123
Product data sheet
countdown value, n xx 03
timer source clock
countdown counter xx 03
02 01 03 02 01 03 02 01 03
TE
TF
INT
n
n
duration of first timer period after
enable may range from n − 1 to n + 1
001aaf906
In this example it is assumed that the timer flag is cleared before the next countdown period
expires and that the pin INT is set to pulsed mode.
Fig 15. General countdown timer behavior
If a new value of n is written before the end of the current timer period, then this value will
take immediate effect. NXP does not recommend changing n without first disabling the
counter (by setting bit TE = 0). The update of n is asynchronous to the timer clock,
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 15 July 2013
© NXP B.V. 2013. All rights reserved.
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