PCF2123U/5GA/1 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF2123U/5GA/1' PDF : 63 Pages View PDF
NXP Semiconductors
PCF2123
SPI Real time clock/calendar
8.7 Interrupt output
An active LOW interrupt signal is available at pin INT. Operation is controlled via the bits
of register Control_2. Interrupts may be sourced from four places: second and minute
timer, countdown timer, alarm function or offset function.
With bit TI_TP, the timer generated interrupts can be configured to either generate a pulse
or to follow the status of the interrupt flags (bits TF and MSF). Correction interrupt pulses
are always 1⁄128 second long. Alarm interrupts always follow the condition of AF.
SI
SECONDS COUNTER
MINUTES COUNTER
MI
from interface:
clear MSF
TE
COUNTDOWN COUNTER
MSF: MINUTE
SECOND FLAG
SET
CLEAR
TF: TIMER
SET
CLEAR
to interface:
read MSF
0
PULSE
1
GENERATOR 1
TRIGGER
CLEAR
TI_TP
to interface:
read TF
0
PULSE
1
GENERATOR 2
TRIGGER
from interface:
clear TF
set alarm
flag, AF
from interface:
clear AF
offset circuit: add/substract
1/64 Hz pulse
from interface:
set CIE
AF: ALARM
FLAG
SET
CLEAR
CLEAR
to interface:
read AF
PULSE
GENERATOR 3
TRIGGER
CLEAR
When bits SI, MI, TIE, AIE, and CIE are all disabled, pin INT will remain high-impedance.
Fig 16. Interrupt scheme
SI MI
TIE
AIE
CIE
INT
E.G.AIE
0
1
001aai555
Remark: Note that the interrupts from the four sources are wired-OR, meaning they will
mask one another (see Figure 16).
PCF2123
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 15 July 2013
© NXP B.V. 2013. All rights reserved.
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