PCF2123U/5GA/1 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF2123U/5GA/1' PDF : 63 Pages View PDF
NXP Semiconductors
PCF2123
SPI Real time clock/calendar
9. 3-line serial interface
Data transfer to and from the device is made via a 3-wire SPI-bus (see Table 42). The
data lines for input and output are split. The data input and output lines can be connected
together to facilitate a bidirectional data bus. The chip enable signal is used to identify the
transmitted data. Each data transfer is a byte, with the Most Significant Bit (MSB) sent first
(see Figure 24).
Table 42. Serial interface
Symbol Function
CE
chip enable input
SCL
SDI
SDO
serial clock input
serial data input
serial data output
Description
when LOW, the interface is reset; pull-down resistor
included; active input may be higher than VDD, but may not
be wired permanently HIGH
when CE is LOW, this input may float; input may be higher
than VDD
when CE is LOW, input may float; input may be higher than
VDD; input data is sampled on the rising edge of SCL
push-pull output; drives from VSS to VDD; output data is
changed on the falling edge of SCL; will be high-Z when not
driving; may be connected directly to SDI
SDI
SDO
SDI
SDO
two wire mode
Fig 23. SDI, SDO configurations
single wire mode
001aai560
The transmission is controlled by the active HIGH chip enable signal CE. The first byte
transmitted is the command byte. Subsequent bytes will be either data to be written or
data to be read. Data is sampled on the rising edge of the clock and transferred internally
on the falling edge.
data bus
COMMAND
DATA
DATA
DATA
chip enable
Fig 24. Data transfer overview
001aaf914
The command byte defines the address of the first register to be accessed and the
read/write mode. The address counter will auto increment after every access and will
rollover to zero after the last register is accessed. The read/write bit (R/W) defines if the
following bytes will be read or write information.
PCF2123
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 15 July 2013
© NXP B.V. 2013. All rights reserved.
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