NXP Semiconductors
PCF2123
SPI Real time clock/calendar
In Figure 26, the Months and Years registers are read. In this example, pins SDI and SDO
are not connected together. For this configuration, it is important that pin SDI is never left
floating. It must always be driven either HIGH or LOW. If pin SDI is left open, high IDD
currents may result. Short transition periods in the order of 200 ns will not cause any
problems.
9.1 Interface watchdog timer
During read/write operations, the time counting circuits are frozen. To prevent a situation
where the accessing device becomes locked and does not clear the interface by setting
pin CE LOW, the PCF2123 has a built in watchdog timer. Should the interface be active
for more than 1 s from the time a valid subaddress is transmitted, then the PCF2123 will
automatically clear the interface and allow the time counting circuits to continue counting.
CE must return LOW once more before a new data transfer can be executed.
CE
data
WD timer
time
counters
tw(CE) < 1 s
valid sub-address data data data
WD timer running
running
time counters frozen
a. Correct data transfer: read or write
running
001aai563
CE
data
1 s < tw(CE) < 2 s
data transfer fail
valid sub-address data data data
WD timer
time
counters
running
WD timer running
time counters frozen
b. Incorrect data transfer: read or write
Fig 27. Interface watchdog timer
WD trips
running
001aai564
The watchdog is implemented to prevent the excessive loss of time due to interface
access failure e.g. if main power is removed from a battery backed-up system during an
interface access.
Each time the watchdog period is exceeded, 1 s will be lost from the time counters. The
watchdog will trigger between 1 s and 2 s after receiving a valid subaddress.
PCF2123
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 15 July 2013
© NXP B.V. 2013. All rights reserved.
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