PCF2127 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF2127' PDF : 101 Pages View PDF
NXP Semiconductors
PCF2127
Accurate RTC with integrated quartz crystal for industrial applications
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Fig 18. Power-On Reset Override (PORO) sequence, valid for both I2C-bus and SPI-bus
Once the override mode is entered, the device is immediately released from the reset
state and the set-up operation can commence.
The PORO mode is cleared by writing logic 0 to POR_OVRD. POR_OVRD must be
logic 1 before a re-entry into the override mode is possible. Setting POR_OVRD logic 0
during normal operation has no effect except to prevent accidental entry into the PORO
mode.
8.9 Time and date function
Most of these registers are coded in the Binary Coded Decimal (BCD) format.
8.9.1 Register Seconds
Table 27. Seconds - seconds and clock integrity register (address 03h) bit allocation
Bits labeled as X are undefined at power-on and unchanged by subsequent resets.
Bit
7
6
5
4
3
2
1
0
Symbol
OSF
SECONDS (0 to 59)
Reset
value
1
X
X
X
X
X
X
X
Table 28. Seconds - seconds and clock integrity register (address 03h) bit description
Bits labeled as X are undefined at power-on and unchanged by subsequent resets.
Bit
Symbol
Value
Place value Description
7
OSF
0
-
clock integrity is guaranteed
1
-
clock integrity is not guaranteed:
oscillator has stopped and chip reset has occurred
since flag was last cleared
6 to 4
SECONDS
0 to 5
ten’s place actual seconds coded in BCD format
3 to 0
0 to 9
unit place
PCF2127
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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