PCF2127 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF2127' PDF : 101 Pages View PDF
NXP Semiconductors
PCF2127
Accurate RTC with integrated quartz crystal for industrial applications
Table 86.
Symbol
SDA/CE
Serial interface
Function
chip enable input;
active LOW
SCL
serial clock input
SDI
serial data input
SDO
serial data output
Description
[1] when HIGH, the interface is reset;
input may be higher than VDD
when SDA/CE is HIGH, input may float;
input may be higher than VDD
when SDA/CE is HIGH, input may float;
input may be higher than VDD;
input data is sampled on the rising edge of
SCL
push-pull output;
drives from VSS to Voper(int) (VBBS);
output data is changed on the falling edge of
SCL
[1] The chip enable must not be wired permanently LOW.
9.1.1 Data transmission
The chip enable signal is used to identify the transmitted data. Each data transfer is a
whole byte, with the Most Significant Bit (MSB) sent first.
The transmission is controlled by the active LOW chip enable signal SDA/CE. The first
byte transmitted is the command byte. Subsequent bytes are either data to be written or
data to be read (see Figure 37).
GDWDEXV
&200$1'
'$7$
'$7$
'$7$
6'$&(
Fig 37. Data transfer overview
DDD
The command byte defines the address of the first register to be accessed and the
read/write mode. The address counter will auto increment after every access and will
reset to zero after the last valid register is accessed. The R/W bit defines if the following
bytes are read or write information.
Table 87. Command byte definition
Bit
Symbol
Value
7
R/W
0
1
6 to 5 SA
01
4 to 0 RA
00h to 1Dh
Description
data read or write selection
write data
read data
subaddress;
other codes will cause the device to ignore
data transfer
register address
PCF2127
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 December 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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