PCF2129T View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF2129T' PDF : 73 Pages View PDF
NXP Semiconductors
PCF2129T
Accurate RTC with integrated quartz crystal for industrial
The setting of the PORO mode requires that POR_OVRD in register Control_1 is set
logic 1 and that the signals at the interface pins SDA/CE and SCL are toggled as
illustrated in Figure 12. All timings shown are required minimum.
power up
8 ms
SDA/CE
minimum 500 ns
minimum 2000 ns
SCL
reset override
001aaj326
Fig 12. Power-On Reset Override (PORO) sequence, valid for both I2C-bus and SPI-bus
Once the override mode is entered, the device is immediately released from the reset
state and the set-up operation can commence.
The PORO mode is cleared by writing logic 0 to POR_OVRD. POR_OVRD must be
logic 1 before a re-entry into the override mode is possible. Setting POR_OVRD logic 0
during normal operation has no effect except to prevent accidental entry into the PORO
mode.
PCF2129T
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 12 February 2013
© NXP B.V. 2013. All rights reserved.
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