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PCF85133U/2DA/1 View Datasheet(PDF) - NXP Semiconductors.

Part Name
Description
MFG CO.
PCF85133U/2DA/1
NXP
NXP Semiconductors. NXP
'PCF85133U/2DA/1' PDF : 41 Pages View PDF
NXP Semiconductors
PCF85133
Universal LCD driver for low multiplex rates
13. Dynamic characteristics
Table 21. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
Clock
Internal: output pin CLK
fclk
clock frequency
ffr
frame frequency
External: input pin CLK
FF = VDD
FF = VSS
FF = VDD
FF = VSS
[1][2] 1440
[1][2] 1920
60
80
1970
2640
82
110
2640
3600
110
150
fclk(ext)
external clock frequency
tclk(H)
HIGH-level clock time
tclk(L)
LOW-level clock time
Synchronization: input pin SYNC
[2] 800
-
130
-
130
-
3600
-
-
tPD(SYNC_N) SYNC propagation delay
tSYNC_NL SYNC LOW time
Outputs: pins BP0 to BP3 and S0 to S79
-
30
-
1
-
-
tPD(drv)
driver propagation delay
I2C-bus: timing[3]
VLCD = 5 V
-
-
30
Pin SCL
fSCL
tHIGH
tLOW
Pin SDA
SCL clock frequency
HIGH period of the SCL clock
LOW period of the SCL clock
-
-
400
0.6
-
-
1.3
-
-
tSU;DAT
data set-up time
tHD;DAT
data hold time
Pins SCL and SDA
100
-
-
0
-
-
tBUF
bus free time between a STOP and
START condition
1.3
-
-
tSU;STO
tHD;STA
tSU;STA
set-up time for STOP condition
hold time (repeated) START condition
set-up time for a repeated START
condition
0.6
-
-
0.6
-
-
0.6
-
-
tr
rise time of both SDA and SCL signals fSCL = 400 kHz
-
-
0.3
fSCL < 125 kHz
-
-
1.0
tf
fall time of both SDA and SCL signals
-
-
0.3
Cb
capacitive load for each bus line
-
-
400
tw(spike)
spike pulse width
on bus
-
-
50
Unit
Hz
Hz
Hz
Hz
Hz
s
s
ns
s
s
kHz
s
s
ns
ns
s
s
s
s
s
s
s
pF
ns
[1] Typical output duty cycle of 50 %.
[2]
The corresponding frame frequency is
ffr
=
f--c---l--k .
24
[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD. For I2C-bus timings see Figure 22.
PCF85133
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 4 July 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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