PCF85133U/2DA/1 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF85133U/2DA/1' PDF : 41 Pages View PDF
NXP Semiconductors
PCF85133
Universal LCD driver for low multiplex rates
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(1) Is master (OSC connected to VSS).
(2) Is slave (OSC connected to VDD).
Fig 23. Cascaded PCF85133 configuration
DDM
For display sizes that are not multiple of 320 elements, a mixed cascaded system can be
considered containing only devices like PCF85133 and PCF8532. Depending on the
application, one must take care of the software command and pin connection
compatibility.
Only one master but multiple slaves are allowed in a cascade. All devices in the cascade
have to use the same clock whether it is supplied externally or provided by the master.
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCF85133s. This synchronization is guaranteed after the power-on reset. The only time
that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in
adverse electrical environments, or by the definition of a multiplex mode when
PCF85133s with different SA0 levels are cascaded).
SYNC is organized as an input/output pin; The output selection is realized as an
open-drain driver with an internal pull-up resistor. A PCF85133 asserts the SYNC line at
the onset of its last active backplane signal and monitors the SYNC line at all other times.
If synchronization in the cascade is lost, it is restored by the first PCF85133 to assert
SYNC. The timing relationships between the backplane waveforms and the SYNC signal
for the various drive modes of the PCF85133 are shown in Figure 24.
PCF85133
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 4 July 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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