PCF8531U/2DA/1 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'PCF8531U/2DA/1' PDF : 51 Pages View PDF
NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
[1] As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD, the user must ensure,
while setting the VOP register and selecting the temperature compensation, that the VLCD maximum limit of 9 V will never be exceeded
under all conditions and including all tolerances.
[2] LCD outputs are open circuit, inputs at VDD or VSS; bus inactive.
[3] VDD1 to VDD3 = 2.85 V; VLCD = 7.0 V; voltage multiplier = 3 × VDD; fosc = 34 kHz.
[4] VDD1 to VDD3 = 2.75 V; VLCD = 9.0 V; fosc = 34 kHz.
[5] VDD1 to VDD3 = 2.75 V; VLCD = 3.5 V; fosc = 34 kHz.
[6] Resets all logic when VDD1 < VPOR.
[7] Iload ≤ 50 μA; outputs are tested one at a time.
[8] VLCD ≤ 7.7 V.
14. Dynamic characteristics
Table 16. Dynamic characteristics
VDD1 = 1.8 V (1.9 V) to 5.5 V; VDD2 and VDD3 = 2.5 V to 4.5 V; VSS1 = VSS2 = 0 V; VDD1 to VDD3 ≤ VLCD ≤ 9.0 V;
Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ
Max
ffr(LCD)
LCD frame frequency
fosc
oscillator frequency
fclk(ext)
external clock frequency
tw(RESL)
RES LOW pulse width
tsu(RESL) RES LOW set-up time
Serial bus interface (see Figure 22)[3]
VDD = 3.0 V
[1] 40
66
135
20
34
65
20
-
65
[2] 300
-
-
-
-
30
fSCL
SCL clock frequency
0
-
400
tLOW
LOW period of the SCL clock
1.3
-
-
tHIGH
HIGH period of the SCL clock
0.6
-
-
tSU;DAT
data set-up time
100
-
-
tHD;DAT
data hold time
0
-
0.9
tr
rise time of both SDA and SCL signals
[4] 20 + 0.1Cb -
0.3
tf
fall time of both SDA and SCL signals
[4] 20 + 0.1Cb -
0.3
Cb
capacitive load for each bus line
-
-
400
tSU;STA
set-up time for a repeated START condition
0.6
-
-
tHD;STA
hold time (repeated) START condition
0.6
-
-
tSU;STO
set-up time for STOP condition
0.6
-
-
tSP
pulse width of spikes that must be
suppressed by the input filter
on bus
-
-
50
tBUF
bus free time between a STOP and START
condition
1.3
-
-
Unit
Hz
kHz
kHz
ns
μs
kHz
μs
μs
ns
ns
μs
μs
pF
μs
μs
μs
ns
μs
[1] ffr = fclk(ext)/480 or fosc/480.
[2] A reset is generated if tw(RESL) > 3 ns (see Figure 21).
[3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH, with an
input voltage swing of VSS to VDD.
[4] Cb = total capacitance of one bus line in pF.
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 16 May 2011
© NXP B.V. 2011. All rights reserved.
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