NXP Semiconductors
PCF8531
34 x 128 pixel matrix driver
15. Application information
15.1 Typical system configuration
VLCD
VDD1 to VDD3
VDD(I2C)
HOST
Rpu Rpu MICROPROCESSOR/
MICROCONTROLLER
PCF8531
128 column drivers
34 row drivers
LCD PANEL
VSS
RES
SCL
SDA
VSS1, VSS2
Fig 29. Typical system configuration
VSS1,
VSS2
mgs483
The host microprocessor/microcontroller and the PCF8531 are both connected to the
I2C-bus. The SDA and SCL lines must be connected to the positive power supply via
pull-up resistors. The internal oscillator requires no external components. The appropriate
intermediate biasing voltage for the multiplexed LCD waveforms are generated on-chip.
The only other connections required to complete the system are to the power supplies
(VDD, VSS, and VLCD) and suitable capacitors for decoupling VLCD and VDD.
15.2 Power supply connections for internal VLCD generation
1.8 V (1.9 V) to 5.5 V
1 μF
2.5 V to 4.5 V
1 μF
VDD1
VDD2
VDD3
2.5 V to 4.5 V
1 μF
VDD1
VDD2
VDD3
GND
VSS1
VSS2
013aaa354
GND
VSS1
VSS2
013aaa355
Fig 30. Recommended VDD connections for internal VLCD generation
PCF8531
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 16 May 2011
© NXP B.V. 2011. All rights reserved.
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