PCF8536AT/1 View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

MFG CO.

PCF8536AT/1

Universal LCD driver for low multiplex rates including a 6 channel PWM generator

NXP Semiconductors. 

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NXP Semiconductors

PCF8536

Universal LCD low multiplex driver with 6 channel PWM generator

9.3 SPI-bus interface

Data transfer to the device is made via a 3 line SPI-bus (see Table 40). There is no output

data line. The SPI-bus is initialized whenever the chip enable line pin CE is inactive.

Table 40.

Symbol

CE

SCL

SDI

Serial interface

Function

chip enable input[1]; active LOW

serial clock input

serial data input

Description

when HIGH, the interface is reset

input may be higher than VDD

input may be higher than VDD; input data is

sampled on the rising edge of SCL

[1] The chip enable must not be wired permanently LOW.

9.3.1 Data transmission

The chip enable signal is used to identify the transmitted data. Each data transfer is a byte

with the Most Significant Bit (MSB) sent first.

The transmission is controlled by the active LOW chip enable signal CE. The first byte

transmitted is the subaddress byte.

data bus

SUBADDRESS

DATA

DATA

DATA

CE

Fig 38. Data transfer overview

013aaa464

The subaddress byte opens the communication with a read/write bit and a subaddress.

The subaddress is used to identify multiple devices on one SPI-BUS.

Table 41. Subaddress byte definition

Bit

Symbol

Value

7

R/W

0

1

6 to 5 SA

01

4 to 0 -

Description

data read or write selection

write data

read data

subaddress; other codes will cause the device

to ignore data transfer

unused

After the subaddress byte, a control byte follows (see Section 9.1 on page 46).

PCF8536

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 6 October 2011

© NXP B.V. 2011. All rights reserved.

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