PCF8813 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'PCF8813' PDF : 72 Pages View PDF
Philips Semiconductors
(67 + 1) × 102 pixels matrix LCD driver
Product speciï¬cation
PCF8813
handbook, full pagewidth
OTP slice
SHIFT
REGISTER
FLIP-FLOP
SHIFT
REGISTER
DATA
INPUT
read data
from the
OTP cell
write data
to the
OTP cell
OTP CELL
DATA TO THE CIRCUIT FOR
CONFIGURATION AND CALIBRATION
SHIFT
REGISTER
OTP CELLs
MGU289
Fig.48 Basic OTP architecture.
17.4.2 OPERATIONS
The OTP architecture allows the following operations:
• The OTP circuit in the PCF8813 is initialized when a
reset is initiated. After the reset initiation, OTP circuits
can be disabled only by sending the disable OTP
command.
• Reading data from the OTP cells. The content of the
non-volatile OTP cells is transferred to the shift register
where it may affect operation of the PCF8813.
• Writing data to the OTP cells. All 9 bits of data are
shifted first into the shift register via the serial interface.
Then the content of the shift register is transferred to the
OTP cells (there are some limitations related to storing
data in these cells; see Section 17.6).
• Checking calibration without writing to the OTP cells.
Shifting data into the shift register allows the effects of
the VLCD voltage to be observed.
All OTP circuitry of the PCF8813 is enabled until the
disable OTP command is given. Once enabled, the
reading of data from the OTP cells is initiated by either:
• Exit from Power-down mode
• The Refresh command (power control). This command
works only when the driver is not in Power-down.
In both cases, the time required for the reading operation
to complete is up to 5 ms.
The shifting of data into the shift register is performed in
the special mode MM. In the PCF8813, the MM mode is
entered through the MM command. Once in the
MM mode, the data is shifted into the shift register via any
of the interfaces at the rate of 1-bit per command. After
transmitting the last (9th) bit and exiting the MM mode, the
interface is again in the normal mode and all other
commands can be sent. Care should be taken that 9 bits
of data (or a multiple of 9) are always transferred before
exiting the MM mode, otherwise the bits will be in the
wrong positions.
The value of the seal bit in the shift register is always zero
at reset (also applies to all other bits). To make sure the
security feature works correctly, the MM command is
disabled until a refresh has been made. Once a refresh is
completed, the seal bit value in the shift register is valid
and permission to enter MM mode can thus be
determined.
The 9 bits are shifted into the shift register in a predefined
order: first 5 bits of VCAL[4:0], followed by 3 bits for MF[2:0]
and then the seal bit. The MSB is always first, that is the
first bit shifted is VCAL[4] and the seal bit is the last bit.
2004 Mar 05
51
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