Philips Semiconductors
(67 + 1) Γ 102 pixels matrix LCD driver
Product speciο¬cation
PCF8813
SYMBOL
PARAMETER
CONDITIONS
MIN.
3-line and 4-line SPI and serial interface; VDD1 = 1.8 to 3.3 V; Figs 41 to 44; note 5
fSCLK
SCLK frequency
β
Tcyc
SCLK cycle time
111
tPWH1
SCLK pulse width HIGH
45
tPWL1
SCLK pulse width LOW
45
tPWH2
SCE minimum HIGH time
50
tS1
SDATA set-up time
50
tH1
SDATA hold time
50
tS2
SCE set-up time
60
tH2
SCE hold time
45
tS3
data/command set-up time
50
tH3
data/command hold time
50
t1
SDOUT access time
β
t2
SDOUT disable time
note 6
β
t3
SCE hold time
50
t4
SDOUT disable time
note 7
β
Cb
capacitive load for SDOUT
note 8
β
Rb
series resistance for SDOUT
note 8
β
I2C-bus interface in Fast-mode; VDD1 = 1.7 to 3.3 V; Fig.45
fSCL
SCL clock frequency
0
tLOW
SCL clock low period
1.3
tHIGH
SCL clock high period
0.6
tSU;DAT
data set-up time
100
tHD;DAT
data hold time
0
cb
capacitive load represented by
β
each bus line
tSU;STA
set-up time for a repeated START
0.6
condition
tHD;STA
START condition hold time
0.6
tSU;STO
set-up time for STOP condition
0.6
tSP
tolerable spike width on bus
note 9
β
I2C-bus interface in Hs-mode; VDD1 = 1.7 to 3.3 V; Fig.46
fSCLH
SCLH clock frequency
0
tSU;STA
set-up time (repeated) START
160
condition
tHD;STA
hold time (repeated) START
160
condition
tLOW
LOW period of the SCLH clock
160
tHIGH
HIGH period of the SCLH clock
60
tSU;DAT
data set-up time
10
TYP.
β
β
β
β
β
β
β
β
β
β
β
β
β
β
β
β
β
β
β
β
β
β
β
β
β
β
β
β
-
β
β
β
β
MAX. UNIT
9
MHz
β
ns
β
ns
β
ns
β
ns
β
ns
β
ns
β
ns
β
ns
β
ns
β
ns
80
ns
80
ns
β
ns
80
ns
30
pF
500
β¦
400
kHz
β
Β΅s
β
Β΅s
β
ns
0.9
Β΅s
400
pF
β
Β΅s
β
Β΅s
β
Β΅s
50
ns
3.4
MHz
β
ns
β
ns
β
ns
β
ns
β
ns
2004 Mar 05
41