C3 SCSP Flash Memory
5.8
Flash Reset Operations
Figure 8.
AC Waveform: Reset Operation
RP# (P) VIH
VIL
t PLPH
(A) Reset during Read Mode
tPHQV
ttPPHHWELL
RP# (P) VIH
Abort
Complete
t PLRH
t PHQV
t PHWL
t PHEL
VIL
t PLPH
(B) Reset during Program or Block Erase, t PLPH < t PLRH
RP# (P) VIH
VIL
Abort Deep
Complete Power-
t PLRH
Down
t PHQV
t PHWL
t PHEL
t PLPH
(C) Reset Program or Block Erase, t PLPH > t PLRH
Table 17.
Reset Specifications(1)
Symbol
Parameter
Note
F-VCC 2.7 V – 3.3 V
Min
Max
Unit
tPLPH
F-RP# Low to Reset during Read (If F-RP# is tied
to VCC, this specification is not applicable)
2,4
100
ns
tPLRH1
F-RP# Low to Reset during Block Erase
3,4
22
µs
tPLRH2
F-RP# Low to Reset during Program
3,4
12
µs
Notes:
1.
See Section 2.1.4, “Flash Reset” on page 13 for a full description of these conditions.
2.
If tPLPH is < 100 ns the device may still reset but this is not guaranteed.
3.
If F-RP# is asserted while a block erase or word program operation is not executing, the reset will
complete within 100 ns.
4.
Sampled, but not 100% tested.
26 Aug 2005
36
Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family
Order Number: 252636, Revision: 004
Datasheet