PF38F1602CT70 View Datasheet(PDF) - Intel
Part Name
Description
MFG CO.
'PF38F1602CT70' PDF : 75 Pages View PDF
C3 SCSP Flash Memory
Table 19.
SRAM AC Characteristics—Write Operations(1,2)
Density 2/4/8-Mbit
#
Sym
Parameter
Volt 2.7 V – 3.3 V Unit
Note Min Max
W8 tWR
Write Recovery
5
0
–
ns
W9 tBW
S-UB#, S-LB# Setup to S-WE# (S-CS1#) Going High
60
–
ns
Notes:
1.
See Figure 10 “AC Waveform: SRAM Write Operations” on page 39.
2.
A write occurs during the overlap (tWP) of low S-CS1# and low S-WE#. A write begins when S-CS1#
goes low and S-WE# goes low with asserting S-UB# or S-LB# for single byte operation or
simultaneously asserting
S-UB# and S-LB# for double byte operation. A write ends at the earliest transition when S-CS1# goes
high and S-WE# goes high. The tWP is measured from the beginning of write to the end of write.
3.
tAS is measured from the address valid to the beginning of write.
4.
tWP is measured from S-CS1# going low to end of write.
5.
tWR is measured from the end of write to the address change. tWR applied in case a write ends as S-
CS1# or S-WE# going high.
Figure 10. AC Waveform: SRAM Write Operations
VIH
ADDRESSES (A)
VIL
VIH
CS1# (E1) VIL
VIH
CS2 (E2) VIL
OE# (G) VIH
VIL
VIH
WE# (W)
VIL
VOH
DATA (D/Q)
VOL
VIH
UB#, LB#
VIH
Standby
Device
Address Selection
Address Stable
W1
High Z
W2
W6
W5
W3
W4
Data In
W9
W8
W7
High Z
Datasheet
Intel® Advanced+ Boot Block Flash Memory (C3) SCSP Family
Order Number: 252636, Revision: 004
26 Aug 2005
39
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