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18-Bit Universal Bus Driver
with 3-State Outputs
Product Features
• Very high-speed, low-noise universal bus driver with
embedded resistor outputs
• Meets PC133 SDRAM Registered DIMM specification
• Implements output impedance control for low-noise and
heavy-load applications
• Fast Propagation Delay:
2.5ns max. for 50pF test load
• VCC = 3.3V or 2.5V or 1.8V
• Packaging (Pb-free and Green available):
– 56-pin, 240 mil wide plastic TSSOP (A)
Product Pin Configuration
NC 1
NC 2
Y1 3
GND 4
Y2 5
Y3 6
VDD 7
Y4 8
Y5 9
Y6 10
GND 11
Y7 12
Y8 13
Y9 14
Y10 15
Y11 16
Y12 17
GND 18
Y13 19
Y14 20
Y15 21
VDD 22
Y16 23
Y17 24
GND 25
Y18 26
OE 27
LE 28
56 GND
55 NC
54 A1
53 GND
52 A2
51 A3
50 VDD
49 A4
48 A5
47 A6
46 GND
45 A7
44 A8
43 A9
42 A10
41 A11
40 A12
39 GND
38 A13
37 A14
36 A15
35 VDD
34 A16
33 A17
32 GND
31 A18
30 CLK
29 LE
Product Description
Data flow from A to Y is controlled by Output Enable (OE). The device
operates in the transparent mode when LE is HIGH. The A data is
latched if CLK is held at a high or low logic level. If LE is LOW, the
A-bus is stored in the latch/flip-flop on the low-to-high transition of
CLK. When OE is HIGH, the outputs are in the high-impedance state.
The PI74AVC16835 bus driver is designed to drive an array of 133
MHz synchronous memory chips, with minimal undershoot/
overshoot noise, and to meet the input signal rise/fall time requirement
of memory chips.
The output drivers of this part have an embedded series-resistor. For
DIMM module design, no external series termination resistors near
the buffer drivers or any other termination resistors are required. This
feature simplifies DIMM module layout design, and results in cost
savings.
09-0003
1
PS8373G
10/27/09