PIC10LF320 View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC10LF320' PDF : 210 Pages View PDF
PIC10(L)F320/322
10.0 I/O PORT
Depending on which peripherals are enabled, some or
all of the pins may not be available as general purpose
I/O. In general, when a peripheral is enabled on a port
pin, that pin cannot be used as a general purpose
output. However, the pin can still be read.
PORTA has three standard registers for its operation.
These registers are:
• TRISA register (data direction)
• PORTA register (reads the levels on the pins of
the device)
• LATA register (output latch)
Some ports may have one or more of the following
additional registers. These registers are:
• ANSELA (analog select)
• WPUA (weak pull-up)
The Data Latch (LATA register) is useful for read-
modify-write operations on the value that the I/O pins
are driving.
A write operation to the LATA register has the same
effect as a write to the corresponding PORTA register.
A read of the LATA register reads of the values held in
the I/O PORT latches, while a read of the PORTA
register reads the actual I/O pin value.
Ports that support analog inputs have an associated
ANSELA register. When an ANSEL bit is set, the digital
input buffer associated with that bit is disabled.
Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 10-1.
EXAMPLE 10-1: INITIALIZING PORTA
; This code example illustrates
; initializing the PORTA register. The
; other ports are initialized in the same
; manner.
FIGURE 10-1:
I/O PORT OPERATION
Read LATA TRISA
Write LATA
Write PORTA
D
Q
CK
Data Register
Data Bus
Read PORTA
To peripherals
ANSELA
VDD
I/O pin
VSS
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
PORTA
PORTA
LATA
LATA
ANSELA
ANSELA
TRISA
B'00000011'
TRISA
;not required on devices with 1 Bank of SFRs
;Init PORTA
;not required on devices with 1 Bank of SFRs
;
;not required on devices with 1 Bank of SFRs
;digital I/O
;not required on devices with 1 Bank of SFRs
;Set RA<1:0> as inputs
;and set RA<2:3> as
;outputs
2011-2015 Microchip Technology Inc.
DS40001585D-page 67
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