PIC12F1840 View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC12F1840' PDF : 410 Pages View PDF
PIC12(L)F1840
REGISTER 8-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
R/W-0/0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
OSFIF
—
C1IF
EEIF
BCL1IF
—
—
bit 7
U-0
—
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
OSFIF: Oscillator Fail Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Unimplemented: Read as ‘0’
C1IF: Comparator C1 Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
EEIF: EEPROM Write Completion Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
BCL1IF: MSSP Bus Collision Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Unimplemented: Read as ‘0’
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE TMR0IF
INTF
OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA
PS<2:0>
PIE1
TMR1GIE ADIE
RCIE
TXIE
SSP1IE CCP1IE TMR2IE
PIE2
OSFIE
—
C1IE
EEIE
BCL1IE
—
—
PIR1
TMR1GIF ADIF
RCIF
TXIF
SSP1IF CCP1IF TMR2IF
PIR2
OSFIF
—
C1IF
EEIF
BCL1IF
—
—
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts.
Bit 0
IOCIF
TMR1IE
—
TMR1IF
—
Register
on Page
74
151
75
76
77
78
DS41441C-page 78
2011-2012 Microchip Technology Inc.
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