PIC12F1840 View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC12F1840' PDF : 410 Pages View PDF
PIC12(L)F1840
After the “BSF EECON1,WR” instruction, the processor
requires two cycles to set up the write operation. The
user must place two NOP instructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms, only during the cycle in which the write
takes place (i.e., the last word of the block write). This
is not Sleep mode as the clocks and peripherals will
continue to run. The processor does not stall when
LWLO = 1, loading the write latches. After the write
cycle, the processor will resume operation with the third
instruction after the EECON1 WRITE instruction.
FIGURE 11-2:
BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES
75
07
0
EEDATH
EEDATA
6
8
First word of block
to be written
Last word of block
to be written
14
14
14
14
EEADRL<4:0> = 00000 EEADRL<4:0> = 00001
EEADRL<4:0> = 00010
EEADRL<4:0> = 11111
Buffer Register
Buffer Register
Buffer Register
Buffer Register
Program Memory
EXAMPLE 11-4: ERASING ONE ROW OF PROGRAM MEMORY
; This row erase routine assumes the following:
; 1. A valid address within the erase block is loaded in ADDRH:ADDRL
; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F
BCF
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BSF
BCF
BSF
BSF
INTCON,GIE
EEADRL
ADDRL,W
EEADRL
ADDRH,W
EEADRH
EECON1,EEPGD
EECON1,CFGS
EECON1,FREE
EECON1,WREN
; Disable ints so required sequences will execute properly
; Load lower 8 bits of erase address boundary
; Load upper 6 bits of erase address boundary
; Point to program memory
; Not configuration space
; Specify an erase operation
; Enable writes
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
55h
EECON2
0AAh
EECON2
EECON1,WR
; Start of required sequence to initiate erase
; Write 55h
;
; Write AAh
; Set WR bit to begin erase
; Any instructions here are ignored as processor
; halts to begin erase sequence
; Processor will stop here and wait for erase complete.
; after erase processor continues with 3rd instruction
BCF
EECON1,WREN ; Disable writes
BSF
INTCON,GIE
; Enable interrupts
2011-2012 Microchip Technology Inc.
DS41441C-page 93
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