PIC12(L)F1840
REGISTER 11-6: EECON2: EEPROM CONTROL 2 REGISTER
W-0/0
bit 7
W-0/0
W-0/0
W-0/0
W-0/0
EEPROM Control Register 2
W-0/0
W-0/0
W-0/0
bit 0
Legend:
R = Readable bit
S = Bit can only be set
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
Data EEPROM Unlock Pattern bits
To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the
EECON1 register. The value written to this register is used to unlock the writes. There are specific
timing requirements on these writes. Refer to Section 11.2.2 “Writing to the Data EEPROM
Memory” for more information.
TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM
Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
EECON1 EEPGD CFGS LWLO FREE WRERR WREN
WR
RD
98
EECON2
EEPROM Control Register 2 (not a physical register)
99*
EEADRL
EEADRL<7:0>
97
EEADRH —(1)
EEADRH<6:0
97
EEDATL
EEDATL<7:0>
97
EEDATH
—
—
EEDATH<5:0>
97
INTCON GIE
PEIE TMR0IE INTE
IOCIE TMR0IF INTF
IOCIF
74
PIE2
OSFIE
—
C1IE
EEIE BCL1IE
—
—
—
76
PIR2
OSFIF
—
C1IF
EEIF BCL1IF
—
—
—
78
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Data EEPROM module.
* Page provides register information.
Note 1: Unimplemented, read as ‘1’.
2011-2012 Microchip Technology Inc.
DS41441C-page 99