PIC14000T-04/SS View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC14000T-04/SS' PDF : 153 Pages View PDF
PIC14000
TABLE 4-2: CALIBRATION CONSTANT
ADDRESSES
Address
0FC0h
0FC1h
0FC2h
0FC3h
0FC4h
0FC5h
0FC6h
0FC7h
0FC8h
0FC9h
0FCAh
0FCBh
0FCCh
0FCDh
0FCEh
0FCFh
0FD0h
0FD1h
0FD2h
0FD3h -
0FF8h
0FF9h-Fh
Data
KREF , exponent
KREF , mantissa high byte
KREF , mantissa middle byte
KREF , mantissa low byte
KBG , exponent
KBG , mantissa high byte
KBG , mantissa middle byte
KBG , mantissa low byte
VTHERM , exponent
VTHERM , mantissa high byte
VTHERM , mantissa middle byte
VTHERM , mantissa low byte
KTC , exponent
KTC , mantissa high byte
KTC , mantissa middle byte
KTC , mantissa low byte
FOSC, unsigned byte
reserved
TWDT, unsigned byte
reserved
calibration space checksums
4.2 Data Memory Organization
The data memory (Figure 4-2) is partitioned into two
banks which contain the general purpose registers and
the special function registers. Bank 0 is selected when
the RP0 bit in the STATUS register is cleared. Bank 1
is selected when the RP0 bit in the STATUS register is
set. Each bank extends up to 7Fh (128 bytes). The first
32 locations of each bank are reserved for the Special
Function Registers. Several Special Function
Registers are mapped in both Bank 0 and Bank 1. The
general purpose registers, implemented as static RAM,
are located from address 20h through 7Fh, and A0
through FF.
4.2.1 GENERAL PURPOSE REGISTER FILE
The register file is accessed either directly, or indirectly
through the file select register FSR (Section 4.4).
FIGURE 4-2: REGISTER FILE MAP
File Address
00h Indirect add.(*) Indirect addr.(*) 80h
01h
TMR0
OPTION
81h
02h
PCL
PCL
82h
03h
STATUS
STATUS
83h
04h
FSR
FSR
84h
05h
PORTA
TRISA
85h
06h RESERVED
RESERVED 86h
07h
PORTC
TRISC
87h
08h
PORTD
TRISD
88h
09h
89h
0Ah
PCLATH
PCLATH
8Ah
0Bh
INTCON
INTCON
8Bh
0Ch
PIR1
PIE1
8Ch
0Dh
8Dh
0Eh ADTMRL
PCON
8Eh
0Fh ADTMRH
SLPCON
8Fh
10h
90h
11h
91h
12h
92h
13h
I2CBUF
I2CADD
93h
14h
I2CCON
I2CSTAT
94h
15h
ADCAPL
95h
16h
ADCAPH
96h
17h
97h
18h
98h
19h
99h
1Ah
9Ah
1Bh
PREFA
9Bh
1Ch
PREFB
9Ch
1Dh
CMCON
9Dh
1Eh
MISC
9Eh
1Fh
ADCON0
ADCON1
9Fh
20h
A0h
General
Purpose
Register
7F
(96 Bytes)
General
Purpose
Register
(96 Bytes)
FF
* Not a physical register.
Shaded areas are unimplemented memory locations,
read as ‘0’s.
DS40122B-page 14
Preliminary
© 1996 Microchip Technology Inc.
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