PIC14000T-04/SS View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC14000T-04/SS' PDF : 153 Pages View PDF
7.5.1.3 TRANSMISSION
When the R/W bit of the address byte is set and an
address match occurs, the R/W bit of the I2CSTAT
register is set. The received address is loaded into the
I2CBUF The ACK pulse will be sent on the ninth bit, and
the SCL pin is held low. The transmit data must be
loaded into the I2CBUF register, which also loads the
I2CSR register. Then the SCL pin should be enabled by
setting the CKP bit (I2CCON<4>). The eight data bits
are shifted out on the falling edge of the SCL input. This
ensures that the SDA signal is valid during the SCL
high time (Figure 7-15).
PIC14000
A I2CIF interrupt is generated for each data transfer
byte. The I2CIF bit must be cleared in software, and the
I2CSTAT register is used to determine the status of the
byte. The I2CIF bit is set on the falling edge of the ninth
clock pulse.
As a slave-transmitter, the ACK pulse from the
master-receiver is latched on the rising edge of the
ninth SCL input pulse. If the SDA line was high (not
ACK), then the data transfer is complete. The slave
then monitors for another occurrence of the START bit.
If the SDA line was low (ACK), the transmit data must
be loaded into the I2CBUF register, which also loads
the I2CSR register. Then the SCL pin should be
enabled by setting the CKP bit (I2CCON<4>).
FIGURE 7-15: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
SDA
Receiving Address
R/W = 1
A7 A6 A5 A4 A3 A2 A1
ACK
Transmitting Data ACK
D7 D6 D5 D4 D3 D2 D1 D0
SCL
S
1 23456789
1234 56789
Data in
SCL held low
P
sampled
reswphoilnedCs PtoUI2CIF
I2CIF (PIR1<3>)
BF (I2CSTAT<0>)
cleared in software
I2CBUF is written in software
From I2CIF interrupt
service routine
CKP (I2CCON<4>)
Set bit after writing to I2CBUF
© 1996 Microchip Technology Inc.
Preliminary
DS40122B-page 51
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