PIC14000T-04/SS View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC14000T-04/SS' PDF : 153 Pages View PDF
PIC14000
Caution:
Reading or writing the ADTMR register
during an A/D conversion cycle can pro-
duce unpredictable results and is not
recommended.
Note:
The correct sequence for writing the
ADTMR register is HI byte followed by LO
byte. Reversing this order will prevent the
A/D timer from running.
During conversion one or both of the following events
will occur:
1. capture event
2. timer overflow
In a capture event, the comparator trips when the slope
voltage on the CDAC output exceeds the input voltage,
causing the comparator output to transition from high to
low. This causes a transfer of the current timer count to
the capture register and sets the ADCIF flag
(PIR1<1>).
A CPU interrupt will be generated if bit ADCIE
(PIE1<1>) is set to ‘1’ (interrupt enabled). In addition,
the Global Interrupt Enable and Peripheral Interrupt
Enables (INTCON<7,6>) must also be set. Software is
responsible for clearing the ADCIF flag prior to the next
conversion cycle. Note that this interrupt can only occur
once per conversion cycle.
In a timer overflow condition, the timer rolls over from
FFFFh to 0000h, and a capture overflow flag (OVFIF)
is asserted (PIR1<0>). The timer continues to incre-
ment following a timer overflow. A CPU interrupt can be
generated if bit OVFIE (PIE1<0>) is set (interrupt
enabled). In addition, the Global Interrupt Enable and
Peripheral Interrupt Enables (INTCON<7,6>) must also
be set. Software is responsible for clearing the OVFIF
flag prior to the next conversion cycle.
FIGURE 8-1: A/D BLOCK DIAGRAM
OSC1
0
1
Internal
Oscillator
ADOFF
WRITE_TMR
FOSC
ADRST
(Configuration Bit)
Clock
Stop
Logic
RESERVED
RESERVED
RD7/AN7
RD6/AN6
RD5/AN5
RD4/AN4
Prog. Ref. B
Prog. Ref. A
Temp sensor
SREFLO
SREFHI
Bandgap Ref.
RA3/AN3
RA2/AN2
RA1/AN1
RA0/AN0
AMUXOE
(ADCON0<2>)
15
14
13
12
11
10
9 Analog
8 Mux
7 ~ 1 kohm
6
5
4
3
2
1
0
Note 2
4
RA0/AN0
ADOFF
ADTMRH
A/D Capture
ADCAPH
ADTMRL
ADCAPL
Timer
Overflow
(OVFIF, PIR1<0>)
A/D
Capture Interrupt
(ADCIF, PIR1<1>)
ADCON0<7:4>
~2.5uA~5uA~10uA~20uA
ADOFF
(SLPCON<0>)
CDAC
0.1µF
(nominal)
ADCON1<7:4>
~100 Ω
ADRST (ADCON0<1>)
Note 1
4-Bit Current DAC
Note 1: All current sources are disabled if ADRST = ‘1’
Note 2: Approximately 3.5 microsecond time constant
Internal
Data
Bus
DS40122B-page 58
Preliminary
© 1996 Microchip Technology Inc.
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