PIC18F010T-I View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC18F010T-I' PDF : 176 Pages View PDF
PIC18F010/020
RRNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Rotate Right f (no carry)
[ label ] RRNCF f [ ,d [,a] ]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f<n>) → dest<n-1>,
(f<0>) → dest<7>
N,Z
0100 00da ffff ffff
The contents of register ’f’ are
rotated one bit to the right. If ’d’ is 0,
the result is placed in WREG. If ’d’
is 1, the result is placed back in
register 'f' (default). If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
register f
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Decode
Read
register ’f’
Q3
Process
Data
Q4
Write to
destination
Example 1:
RRNCF REG
Before Instruction
REG = 1101 0111
N
=?
Z
=?
After Instruction
REG =
N
=
Z
=
1110 1011
1
0
Example 2:
RRNCF REG, 0, 0
Before Instruction
WREG = ?
REG = 1101 0111
N
=?
Z
=?
After Instruction
WREG =
REG =
N
=
Z
=
1110 1011
1101 0111
1
0
SETF
Set f
Syntax:
[label] SETF f [,a]
Operands:
0 ≤ f ≤ 255
a ∈ [0,1]
Operation:
FFh → f
Status Affected: None
Encoding:
0110 100a ffff ffff
Description:
The contents of the specified regis-
ter are set to FFh. If ’a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ’a’ is 1, the
Bank will be selected as per the
BSR value.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ’f’
Process
Data
Write
register ’f’
Example:
SETF
REG
Before Instruction
REG
= 0x5A
After Instruction
REG
= 0xFF
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 129
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