PIC18F010T-I View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC18F010T-I' PDF : 176 Pages View PDF
PIC18F010/020
LFSR
Load FSR
Syntax:
[ label ] LFSR f,k
Operands:
0≤f≤2
0 ≤ k ≤ 4095
Operation:
k → FSRf
Status Affected: None
Encoding:
Description:
1110
1111
1110 00ff k11kkk
0000 k7kkk kkkk
The 12-bit literal ’k’ is loaded into
the file select register pointed to
by ’f’
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Q2
Decode
Read literal
’k’ MSB
Decode
Read literal
’k’ LSB
Q3
Process
Data
Process
Data
Q4
Write
literal ’k’
MSB to
FSRfH
Write literal
’k’ to FSRfL
Example:
LFSR FSR2, 0x3AB
After Instruction
FSR2H
=
FSR2L
=
0x03
0xAB
MOVF
Move f
Syntax:
[ label ] MOVF f [ ,d [,a] ]
Operands:
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
Operation:
f → dest
Status Affected: N,Z
Encoding:
0101 00da ffff ffff
Description:
The contents of register ’f’ is moved
to a destination dependent upon
the status of ’d’. If 'd' is 0, the result
is placed in WREG. If 'd' is 1, the
result is placed back in register 'f'
(default). Location 'f' can be any-
where in the 256 byte Bank. If ’a’ is
0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ is 1, the Bank will be selected
as per the BSR value.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Read
register ’f’
Q3
Process
Data
Q4
Write
WREG
Example:
MOVF
Before Instruction
REG
=
WREG
=
N
=
Z
=
After Instruction
REG
=
WREG
=
N
=
Z
=
REG, W
0x22
0xFF
?
?
0x22
0x22
0
0
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 119
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