PIC18F010T-I View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC18F010T-I' PDF : 176 Pages View PDF
PIC18F010/020
RETURN
Return from Subroutine
Syntax:
[ label ] RETURN [s]
Operands:
s ∈ [0,1]
Operation:
(TOS) → PC,
if s = 1
(WS) → W,
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged
Status Affected: None
Encoding:
0000 0000 0001 001s
Description:
Return from subroutine. The
stack is popped and the top of the
stack (TOS) is loaded into the
program counter. If ’s’ = 1, the
contents of the shadow registers
WS, STATUSS and BSRS are
loaded into their corresponding
registers, WREG, STATUS and
BSR. If ’s’ = 0, no update of
these registers occurs (default).
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Decode
No
operation
Q2
No
operation
No
operation
Q3
Process
Data
No
operation
Q4
Pop PC from
stack
No
operation
Example:
RETURN
After Call
PC
= TOS
RETURN FAST
Before Instruction
WRG = 0x04
STATUS = 0x00
BSR = 0x00
After Instruction
WREG =
STATUS =
BSR =
PC
=
0x04
0x00
0x00
TOS
RLCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Rotate Left f through Carry
[ label ] RLCF f [ ,d [,a] ]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f<n>) → dest<n+1>,
(f<7>) → C,
(C) → dest<0>
C,N,Z
0011 01da ffff ffff
The contents of register 'f' are
rotated one bit to the left through
the Carry Flag. If 'd' is 0 the result is
placed in WREG. If 'd' is 1 the
result is stored back in register 'f'
(default). If ’a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ’a’ is 1, the Bank
will be selected as per the BSR
value.
C
register f
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Decode
Q2
Read
register ’f’
Q3
Process
Data
Q4
Write to
destination
Example:
RLCF
REG, W
Before Instruction
REG = 1110 0110
C
=0
N
=?
Z
=?
After Instruction
REG =
WREG =
C
=
N
=
Z
=
1110 0110
1100 1100
1
1
0
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 127
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