PIC18F010T-I View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC18F010T-I' PDF : 176 Pages View PDF
PIC18F010/020
RETFIE
Return from Interrupt
Syntax:
[ label ] RETFIE [s]
Operands:
s ∈ [0,1]
Operation:
(TOS) → PC,
1 → GIE/GIEH or PEIE/GIEL,
if s = 1
(WS) → WREG,
(STATUSS) → STATUS,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged.
Status Affected: None
Encoding:
0000 0000 0001 000s
Description:
Return from Interrupt. Stack is
popped and Top-of-Stack (TOS)
is loaded into the PC. Interrupts
are enabled by setting the either
the high or low priority global
interrupt enable bit. If ’s’ = 1, the
contents of the shadow registers
WS, STATUSS and BSRS are
loaded into their corresponding
registers, WREG, STATUS and
BSR. If ’s’ = 0, no update of
these registers occurs (default).
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Decode
Q2
No
operation
No
operation
No
operation
Q3
No
operation
No
operation
Q4
Pop PC from
stack
Set GIEH or
GIEL
No
operation
Example:
RETFIE 1
After Interrupt
PC
=
WREG
=
BSR
=
STATUS
=
GIE/GIEH, PEIE/GIEL =
TOS
WS
BSRS
STATUSS
1
RETLW
Return Literal to WREG
Syntax:
[ label ] RETLW k
Operands:
0 ≤ k ≤ 255
Operation:
k → W,
(TOS) → PC,
PCLATU, PCLATH are unchanged
Status Affected: None
Encoding:
0000 1100 kkkk kkkk
Description:
W is loaded with the eight bit literal
'k'. The program counter is loaded
from the top of the stack (the return
address). The high address latch
(PCLATH) remains unchanged.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Decode
Q2
Read
literal ’k’
No
operation
No
operation
Q3
Process
Data
No
operation
Q4
Pop PC from
stack, write
to WREG
No
operation
Example:
CALL TABLE
:
TABLE
ADDWF PCL
RETLW k0
RETLW k1
:
:
RETLW kn
; WREG contains table
; offset value
; WREG now has
; table value
; WREG = offset
; Begin table
;
; End of table
Before Instruction
WREG = 0x07
After Instruction
WREG = value of kn
DS41142A-page 126
Preliminary
2001 Microchip Technology Inc.
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