PIC18F010T-I View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC18F010T-I' PDF : 176 Pages View PDF
PIC18F010/020
RCALL
Relative Call
Syntax:
[ label ] RCALL n
Operands:
-1024 ≤ n ≤ 1023
Operation:
(PC) + 2 → TOS,
(PC) + 2 + 2n → PC
Status Affected: None
Encoding:
1101 1nnn nnnn nnnn
Description:
Subroutine call with a jump up to
1K from the current location. First,
return address (PC+2) is pushed
onto the stack. Then, add the 2’s
complement number ’2n’ to the PC.
Since the PC will have incremented
to fetch the next instruction, the
new address will be PC+2+2n.
This instruction is a two-cycle
instruction.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Decode
No
operation
Q2
Read literal
’n’
Push PC to
stack
No
operation
Q3
Process
Data
No
operation
Q4
Write to PC
No
operation
Example:
HERE
RCALL Jump
Before Instruction
PC = Address(HERE)
After Instruction
PC = Address(Jump)
TOS = Address (HERE+2)
RESET
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Reset
[ label ] RESET
None
Reset all registers and flags that
are affected by a MCLR Reset.
All
0000 0000 1111 1111
This instruction provides a way to
execute a MCLR Reset in software.
1
1
Q2
Start
reset
Q3
No
operation
Q4
No
operation
Example:
RESET
After Instruction
Registers = Reset Value
Flags* = Reset Value
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 125
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