PIC18F010T-I/SN View Datasheet(PDF) - Microchip Technology
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MFG CO.
'PIC18F010T-I/SN' PDF : 176 Pages View PDF
4.9 Data Memory Organization
The data memory is implemented as static RAM. Each
register in the data memory has a 12-bit address,
allowing up to 4096 bytes of data memory. Figure 4-6
and Figure 4-7 show the data memory organization for
the PIC18F010/020 devices.
Banking is required to allow more than 256 bytes to be
accessed. The data memory map is divided into 2
banks that contain 256 bytes each. The lower 4 bits of
the Bank Select Register (BSR<3:0>) select which
bank will be accessed. The upper 4 bits for the BSR
are not implemented.
The data memory contains Special Function Registers
(SFR) and General Purpose Registers (GPR). The
SFRs are used for control and status of the controller
and peripheral functions, while GPRs are used for data
storage and scratch pad operations in the user’s appli-
cation. The SFRs start at the last location of Bank 15
(0xFFF) and grow downwards. GPRs start at the first
location of Bank 0 and grow upwards. Any read of an
unimplemented location will read as ’0’s.
The entire data memory may be accessed directly or
indirectly. Direct addressing may require the use of the
BSR register. Indirect addressing requires the use of
the File Select Register (FSR). Each FSR holds a 12-
bit address value that can be used to access any loca-
tion in the Data Memory map, without banking.
The instruction set and architecture allow operations
across all banks. This may be accomplished by indi-
rect addressing, or by the use of the MOVFF instruction.
The MOVFF instruction is a two-word/two-cycle instruc-
tion, that moves a value from one register to another.
To ensure that commonly used registers (SFRs and
select GPRs) can be accessed in a single cycle,
regardless of the current BSR values, an Access Bank
is implemented. A segment of Bank 0 and a segment
of Bank 15 comprise the Access RAM. Section 4.10
provides a detailed description of the Access RAM.
Note: Only 2 banks are implemented, Bank 0 and
Bank 15.
PIC18F010/020
4.9.1
GENERAL PURPOSE REGISTER
FILE
The register file can be accessed either directly or indi-
rectly. Indirect addressing operates through the File
Select Registers (FSR). The operation of indirect
addressing is shown in Section 4.12.
Enhanced MCU devices may have banked memory in
the GPR area. GPRs are not initialized by a Power-on
Reset and are unchanged on all other RESETs.
Data RAM is available for use as GPR registers by all
instructions. Bank 15 (0xF80 to 0xFFF) contains SFRs.
Bank 0 contains GPR registers.
4.9.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers
used by the CPU and Peripheral Modules for control-
ling the desired operation of the device. These regis-
ters are implemented as static RAM. A list of these
registers is given in Figure 4-7 and Figure 4-8.
The SFRs can be classified into two sets: those asso-
ciated with the “core” function and those related to the
peripheral functions. Those registers related to the
“core” are described in this section, while those related
to the operation of the peripheral features are
described in the section of that peripheral feature.
The SFRs are typically distributed among the peripher-
als whose functions they control.
The unused SFR locations will be unimplemented and
read as '0's. See Figure 4-7 for addresses for the
SFRs.
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 31
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