PIC18F010T-I/SN View Datasheet(PDF) - Microchip Technology
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Description
MFG CO.
'PIC18F010T-I/SN' PDF : 176 Pages View PDF
PIC18F010/020
8.2
PIR Registers
The PIR2 register contains the individual flag bits for
the peripheral interrupts.
Note 1: Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
2: User software should ensure the appropri-
ate interrupt flag bits are cleared prior to
enabling an interrupt, and after servicing
that interrupt.
8.3 PIE Registers
The PIE2 register contains the individual enable bits for
the peripheral interrupts. When IPEN = 0, the PEIE bit
must be set to enable any of these peripheral inter-
rupts.
8.4 IPR Registers
The IPR2 register contains the individual priority bits for
the peripheral interrupts. The operation of the priority
bits requires that the Interrupt Priority Enable (IPEN) bit
be set.
8.5 RCON Register
The RCON register contains the bit which is used to
enable prioritized interrupts (IPEN).
REGISTER 8-3:
RCON REGISTER
R/W-0
U-0
IPEN
—
bit 7
U-0
R/W-1
R-1
R-1 R/W-0 R/W-0
—
RI
TO
PD
POR
BOR
bit 0
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (16CXXX compatibility mode)
Unimplemented: Read as '0'
RI: RESET Instruction Flag bit
For details of bit operation see Register 4-1
TO: Watchdog Time-out Flag bit
For details of bit operation see Register 4-1
PD: Power-down Detection Flag bit
For details of bit operation see Register 4-1
POR: Power-on Reset Status bit
For details of bit operation see Register 4-1
BOR: Brown-out Reset Status bit
For details of bit operation see Register 4-1
Legend:
R = Readable bit
W = Writable bit
- n = Value at POR Reset ’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
2001 Microchip Technology Inc.
Preliminary
DS41142A-page 63
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