PIC18LF010T-I View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
'PIC18LF010T-I' PDF : 176 Pages View PDF
PIC18F010/020
4.5 Clocking Scheme/Instruction
Cycle
The clock input (from OSC1) is internally divided by
four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The instruc-
tion is decoded and executed during the following Q1
through Q4. The clocks and instruction execution flow
are shown in Figure 4-4.
FIGURE 4-4:
CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
PC
OSC2/CLKOUT
(Internal Oscillator
mode)
Fetch INST (PC)
Execute INST (PC-2)
Q1 Q2 Q3 Q4
PC+2
Fetch INST (PC+2)
Execute INST (PC)
Q1 Q2 Q3 Q4
PC+4
Fetch INST (PC+4)
Execute INST (PC+2)
Internal
phase
clock
4.6 Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g. GOTO),
then two cycles are required to complete the instruction
(Example 4-2).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register" (IR) in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
2. MOVWF PORTB
TCY0
Fetch 1
TCY1
Execute 1
Fetch 2
3. BRA SUB_1
4. BSF PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
TCY2
Execute 2
Fetch 3
TCY3
TCY4
TCY5
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles, since the fetch
instruction is “flushed” from the pipeline, while the new instruction is being fetched and then executed.
DS41142A-page 28
Preliminary
2001 Microchip Technology Inc.
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