ELAN 8X10
DATA SHEET
PMC-970109
ISSUE 3
PM3350 ELAN 8 X10
8 PORT ETHERNET SWITCH
Memory Interface
60 ns EDO DRAM AC Timing
Parameter
TCKP
TARD
TRAW
TACD
TCAW
TCP
TCPL
TWDS
TWDH
TRDS
TRDH
TREC
Description
MCLK period
Row address stable to MRAS* fall delay
Row address width
Column address stable to CAS* fall delay
Column address width
CAS* period
CAS* low time
Write data setup to CAS* fall
Write data hold to CAS* fall
Read data setup to CAS* fall
Read data hold from CAS* fall
Read data HiZ to write data drive
MIN TYP MAX Units
20
nsec
15
nsec
35
nsec
15
nsec
35
nsec
35
nsec
15
nsec
15
nsec
15
nsec
20
nsec
0
nsec
15
nsec
150 ns EEPROM/EPROM AC Timing
Parameter
Description
MIN
TCKP
MCLK period
TMAOD Max MADDR[17:0] delay from SYSCLK (read, first cycle)
TCEW
Min MCS*[3:0] pulse width
TOEW
Min MRD* pulse width
TMDIS
Min MDATA[31:0] setup to SYSCLK (read, 11th cycle)
TRDH
Min MDATA[31:0] hold from MRD* rise (read, 12th cycle)
(by design, data is latched internally in the cycle before the
rise of MRD*)
TWAW
Min MADDR[17:0] setup to MWE*[3:0] rise
TWAH
Min MADDR[17:0] hold from MWE*[3:0] rise
TWP
Min MWE*[3:0] pulse width (write, second cycle)
TWDS
Min MDATA[31:0] setup to MWE*[3:0] rise
TWDH
Min MDATA[31:0] hold to MWE*[3:0] rise
TYP
20
21
190
190
10
0
190
40
190
180
15
MAX
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY
33