PM5343STXC View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM5343STXC' PDF : 198 Pages View PDF
DATA SHEET
PMC-930303
ISSUE 6
PM5343 STXC
SONET/SDH TRANSPORT OVERHEAD TRANSCEIVER
Address 04H: TLOP Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function
DB2
UBT
APSREG
DZ2
DAPS
DDL
DOW
RDI
Default
0
0
0
0
0
0
0
0
RDI:
The RDI bit controls the insertion of transmit line remote defect indication
(RDI). When RDI is a logic one, line RDI is inserted into the transmit stream.
Line RDI is inserted by transmitting the code 110 in bit positions 6, 7, and 8 of
the K2 byte. Line RDI may also be inserted using the TRDI input (when the
ring control ports are disabled) or using the transmit ring control port (when it
is enabled). When RDI is logic zero, bit 6, 7, and 8 of the K2 byte are not
modified by the transmit line overhead processor.
DOW:
The DOW bit controls the overwriting of the express orderwire byte (E2).
When DOW is logic one, the value sampled on TIN[7:0] during the E2 byte
position is passed through the transmit line overhead processor unaltered, as
though the TDIS input had been sampled high during the E2 byte position in
the incoming frame. The upstream insertion of the express orderwire is thus
accomplished without the use of the TDIS input. Note that only the E2 byte
position is passed unaltered, the remaining 2 (STS-3/STM-1) undefined byte
positions are overwritten with all zeros. This overwriting may be defeated by
using the TDIS input, or by using the UBT bit in this register. When DOW is
logic zero, the express order wire source is nominally the TLOW input (while
TDIS and TTOHEN are both low).
DDL:
The DDL bit controls the overwriting of the line data communications channel
(D4 - D12). When DDL is logic one, the values sampled on TIN[7:0] during
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 56
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