PM6685
Monitoring and protections
The stability of the system depends firstly on the output capacitor zero frequency. The
following condition should be satisfied:
Equation 21
fsw
> k × fZout
=
k
2π × Cout
× Rout
where k is a design parameter greater than 3 and Rout is the ESR of the output capacitor. It
determinates the minimum integrator capacitor value CINT:
Equation 22
CINT
>
gm
2π × ⎜⎛ fsw
⎝k
− fZout
⎟⎞
⎠
×
Vr
VOUT
where gm=50us is the integrator transconductance.
In order to ensure stability it must be also verified that:
Equation 23
CINT
>
gm
2π × fZout
×
Vr
VOUT
In order to reduce ground noise due to load transient on the other section, it is
recommended to add a resistor RINT and a capacitor Cfilt that, together with CINT, realize a
low pass filter (see Figure 36). The cutoff frequency fCUT must be much greater (10 or more
times) than the switching frequency of the section:
Equation 24
RINT
=
1
2π ×
fCUT
×
CINT
CINT
×
+
Cfilt
Cfilt
Due to the capacitive divider (CINT, Cfilt), the ripple voltage at the COMP pin is given by:
Equation 25
VRIPPLEINT
=
VRIPPLEout
×
CINT
CINT + Cfilt
= VRIPPLEout × q
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