PM7382-PI View Datasheet(PDF) - PMC-Sierra
Part Name
Description
MFG CO.
'PM7382-PI' PDF : 330 Pages View PDF
RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
Table 3 – Miscellaneous Interface Signals (58)
Pin Name Type
SYSCLK Input
RSTB
Input
PMCTEST Input
TCK
Input
TMS
Input
TDI
Input
Pin Function
No.
K23 The system clock (SYSCLK) provides timing for
the core logic. SYSCLK is nominally a 50%
duty cycle, 25 to 45 MHz clock.
C22 The active low reset signal (RSTB) signal
provides an asynchronous FREEDM-32P256
reset. RSTB is an asynchronous input. When
RSTB is set low, all FREEDM-32P256 registers
are forced to their default states. In addition,
TD[31:0] are forced high and all PCI output pins
are forced tristate and will remain high or
tristated, respectively, until RSTB is set high.
AB3 The PMC production test enable signal
(PMCTEST) places the FREEDM-32P256 is test
mode. When PMCTEST is set high, production
test vectors can be executed to verify
manufacturing via the test mode interface
signals TA[11:0], TA[12]/TRS, TRDB, TWRB and
TDAT[15:0]. PMCTEST must be tied low for
normal operation.
T23 The test clock signal (TCK) provides timing for
test operations that can be carried out using the
IEEE P1149.1 test access port. TMS and TDI
are sampled on the rising edge of TCK. TDO is
updated on the falling edge of TCK.
T22 The test mode select signal (TMS) controls the
test operations that can be carried out using the
IEEE P1149.1 test access port. TMS is
sampled on the rising edge of TCK. TMS has
an integral pull up resistor.
U21 The test data input signal (TDI) carries test data
into the FREEDM-32P256 via the IEEE P1149.1
test access port. TDI is sampled on the rising
edge of TCK.
TDI has an integral pull up resistor.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 30
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